PCSCFG=PCSCFG_0, MASTER=MASTER_0, SAMPLE=SAMPLE_0, OUTCFG=OUTCFG_0, AUTOPCS=AUTOPCS_0, PCSPOL=PCSPOL_0, PINCFG=PINCFG_0, MATCFG=MATCFG_0, NOSTALL=NOSTALL_0
Configuration Register 1
| MASTER | Master Mode 0 (MASTER_0): Slave mode 1 (MASTER_1): Master mode |
| SAMPLE | Sample Point 0 (SAMPLE_0): Input data is sampled on SCK edge 1 (SAMPLE_1): Input data is sampled on delayed SCK edge |
| AUTOPCS | Automatic PCS 0 (AUTOPCS_0): Automatic PCS generation is disabled 1 (AUTOPCS_1): Automatic PCS generation is enabled |
| NOSTALL | No Stall 0 (NOSTALL_0): Transfers will stall when the transmit FIFO is empty or the receive FIFO is full 1 (NOSTALL_1): Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur |
| PCSPOL | Peripheral Chip Select Polarity 0 (PCSPOL_0): The Peripheral Chip Select pin PCSx is active low 1 (PCSPOL_1): The Peripheral Chip Select pin PCSx is active high |
| MATCFG | Match Configuration 0 (MATCFG_0): Match is disabled 2 (MATCFG_2): 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) 3 (MATCFG_3): 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) 4 (MATCFG_4): 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] 5 (MATCFG_5): 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] 6 (MATCFG_6): 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] 7 (MATCFG_7): 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] |
| PINCFG | Pin Configuration 0 (PINCFG_0): SIN is used for input data and SOUT is used for output data 1 (PINCFG_1): SIN is used for both input and output data 2 (PINCFG_2): SOUT is used for both input and output data 3 (PINCFG_3): SOUT is used for input data and SIN is used for output data |
| OUTCFG | Output Config 0 (OUTCFG_0): Output data retains last value when chip select is negated 1 (OUTCFG_1): Output data is tristated when chip select is negated |
| PCSCFG | Peripheral Chip Select Configuration 0 (PCSCFG_0): PCS[3:2] are enabled 1 (PCSCFG_1): PCS[3:2] are disabled |